The invention relates to a circuit for the encoding and decoding of digital data with an error correction code.
The invention also relates to a digital video recording/reproducing system comprising such a circuit.
In a circuit of this kind, digital data words are formed from a stream of digital data, each data word being encoded according to a particular error correction code (i.e. provided with so-called parity symbols) after which they are stored as code words on a storage medium (upon recording). Should the code words no longer correspond completely to the original code words, due to disturbances or damaging of any kind after recovery from the storage medium (upon reproduction), the redundant information in the parity symbols enables error correction upon decoding. It is often advantageous to use a combination of two error correction codes. To this end, the digital data symbols (such as bytes) can be arranged, for example, in rectangular blocks, so that data words are formed in the horizontal and the vertical direction. The horizontal data words and the vertical data words can then be protected by way of two (possibly different) codes. The codes together are also referred to as a product code. For encoding and decoding it is necessary to store the digital data temporarily block-wise in an external frame memory. In order to enable simple and fast reading and writing in such an external frame memory, accompanied by a low power dissipation and limited use of wiring, it is advantageous if one (standard) memory suffices.